In recent years, compliance with the electro-magnetic compatibility (EMC) is increasingly becoming important in electronic circuits. In addition, the ratio of faster speed signals in an electronic circuit is rapidly increased due to increase in pin counts in recent large scale integrations (LSIs) and increase in the size of ball grid arrays (BGAs). Accordingly, in design of electronic apparatuses, reliable and efficient compliance with the EMC is desired.
A shield pattern is a design technique effective to reduce the radiation noises (electromagnetic noises) in a circuit board. For example, Patent Reference 1 and Patent Reference 2 listed below disclose a technique that automatically generates a shield pattern by automatically generating a ground line (guard pattern, ground guard wiring) around a signal line. In addition, Patent Reference 3 and Patent Reference 4 listed below disclose multi-layered circuit boards having a shield pattern in a layer above or below a signal line.
However, due to scaling and increase in the density of a circuit board, there are more cases in which an element that interferes with generation of a shield (obstruct) in the vicinity of a signal line to be shielded. This is increasingly making generation of a shield pattern completely encircle a signal line to be shielded difficult without causing any clearance error with the nearby obstruct.
In addition, the location of an element as described above that interferes with a shield pattern is often prohibited from being moved for the reason of easy of production and electrical properties. When there is an obstruct the location of which is prohibited from being changed, disposing as many shield patterns as possible around a signal line is desired, without causing any clearance error with this obstruct.    Patent Reference 1: Japanese Laid-Open Patent Publication No. H08-106489    Patent Reference 2: Japanese Laid-Open Patent Publication No. 2003-186931    Patent Reference 3: Japanese Laid-Open Patent Publication No. H05-299878    Patent Reference 4: Japanese Laid-Open Patent Publication No. 2003-198146